In a recent International Technology Roadmap for Semiconductors (ITRS), the Test and Automatic Test Equipment reports that one of the difficulties of the challenge is to detect systemic defects. In Yield Enhancement, this report also points out that the identification of Non-Visual Defects and Process Variations was set to the most important key challenge in the future. The project "An Academic Exploration on Interpreting the Yield and Randomness for Wafer Map Analysis” aims, from the fundamental analysis, (I) to derive a characteristic value to represent the randomness of the spatial appearance, (II) to calculate an equivalent number of defects to represent the combined process integrity, (III) to explore the defect-yield formula for multipartite wafer map, and (IV) to find the discriminant of homogeneity for wafer map analysis. In terms of academics, it is to seek more in-depth verification features, and to analyze the combined effects of more defect-like states and equivalent defect (non-visual defect and process variation) from the mass production wafer maps.
|Effective start/end date||1/08/20 → 31/07/21|
UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This project contributes towards the following SDG(s):
- Wafer Map
- Fatal Defect
- Process Variation
- Yield Analysis
- Monte Carlo Method
- Boomerang Chart
- Defect Number
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