Aging-Aware Low Power Design Reliability Analysis and Optimization Strategies(2/3)

As CMOS technology continuous to scale down, Integrated circuits (ICs) have been wieldy applied to various applications such as remote sensors and smart portable devices due to the benefits of smaller area, higher complexity, and high performance. These applications are usually under limited power budget, which makes low power design as an indispensable technique. On the other hand, high power density and high operating temperature speed-up circuit aging and threaten the integrity of the ICs. To address these problems, low power design techniques and again-aware design methodologies are indispensable in modern IC-design flow. Related techniques are widely investigated and proposed in literature. Although these design techniques can help to reduce power consumption and increase reliability, many crucial challenges in implementation and dynamic operation are still not well resolved. Therefore, in this 3-year proposal, we will deeply study the existing low power design techniques and aging-aware design techniques, find the relevance of them, and propose new integrated methodologies and corresponding computer aided design (CAD) algorithms to efficiently address these crucial challenges. Specifically, the objective of this proposal is to find solutions for the following three crucial problems:(A)NBTI-Aware Wake-Up Strategy for Power-Gated Designs(B)NBTI-Aware Dynamic Voltage Scaling Strategy for Multi-Module Designs(C)Machine-learning Based Circuit Health Estimation Strategy and Algorithms for Recycling Integrated Circuits for ReuseThe contents of this proposal work in concert with the demand of the semiconductor industry. Instead of developing traditional heuristic based solutions, we will propose AI / machine learning based methodologies to efficiently handle designs with large gate counts. Specifically, we will develop wake-up scheduling frameworks and dynamic voltage / frequency scheduling frameworks for NBTI-aware designs, and will propose a machine-learning based circuit health estimation method and algorithms for IC recycling for reuse. The proposed methodologies can be adapt to not only consuming electronic products (ex: hand-held devices) but also industrial production machines (ex: automatic manufactory) to solve the challenges in modern IC design industry.