考量老化且適用於邊緣運算之深度類神經網路加速器設計與優化研究(3/3)

Status	Finished
Effective start/end date	1/08/23 → 31/07/24

A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks
Chen, Y. G., Hsu, C. W., Chiang, H. Y., Hsieh, T. H. & Jou, J. Y., 2021, Proceedings - 34th IEEE International System-on-Chip Conference, SOCC 2021. Qu, G., Xiong, J., Zhao, D., Muthukumar, V., Reza, M. F. & Sridhar, R. (eds.). IEEE Computer Society, p. 278-283 6 p. (International System on Chip Conference; vol. 2021-September).
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions
Chen, Y. G., Chiang, H. Y., Hsu, C. W., Hsieh, T. H. & Jou, J. Y., 2021, Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., p. 290-291 2 p. (Proceedings - International SoC Design Conference 2021, ISOCC 2021).
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
3 Scopus citations

Project Details