應用於三維積體電路可測性及可靠性設計技術-總計畫暨子計畫一:三維積體電路中堆疊式記憶體與晶粒間連接線可測性與可靠性技術

Project Details

Description

Through-silicon-via based three-dimensional (3D) IC is one of IC design technologies. However, testing and reliability issues are two key challenges for the volume production of 3D ICs. Therefore, we attempt to develop important techniques for overcoming those two issues under the grand project entitled “Design-for-Testability and Reliability Techniques for Stacked RAMs and Inter-Die Interconnection in 3D ICs” which including five subprojects. Inter-die interconnection and stacked memory are two key components in 3D ICs, which have a heavy impact on the reliability and quality of 3D ICs.
StatusFinished
Effective start/end date1/05/1531/07/16

Keywords

  • three-dimensional integrated circuit
  • inter-die interconnection
  • stacked memory
  • testing
  • reliability

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