低維度新穎材料、晶圓級製程與關鍵技術整合於建構前瞻半導體元件之研究-低維度新穎材料、晶圓級製程與關鍵技術整合於建構前瞻半導體元件之研究(2/2)

Silicon-based semiconductor materials face physical limitation under scalingdown,thus the low-dimensional semiconductor materials, including 1D material(Carbon nanotube, CNT) and 2D materials (like MoS2, WS2 .etc), are evaluatedas ideal candidates for next-generation semiconductor processes due to theiratomic scale and excellent transportation properties. However, there are stillmany bottlenecks in the integration of 2D semiconductors, including high defectsin these 1D-/2D-materials, lack of wafer-level synthesis technology, high metalcontact resistance, incompatibility with current IC processes, etc. This studyforms a cross-domain team, proposes innovative thinking aim to break throughthese bottlenecks, and the integrated plan consists of four sub-projects: subproject#1 aims to develop novel 1D/2D semiconductor materials with acontrollable synthesis technology, to achieve the controllability assembly ofsemiconducting CNTs as channel materials and the single-crystal domaincontrolled synthesis for 2D materials. Sub-project #2 aims to develop newtechnology on low-temperature and in-situ growth of 2D materials with wafer-leveland to achieve a platform for versatile device integration. Sub-project #3 aims todevelop the key technologies for integrating low-dimensional semiconductormaterials and their related devices, the goal is to (1)develop wafer-level rapiddefect detection on 2D material, (2) 2D material applied in the BEOL processsuch as the ultra-Low-K dielectric materials and advanced barrier layer ininterconnection,(3) through the quantum transport calculations to provide thedesign protocols for 2D material synthesis and device architecture. Sub-project#4will study the heterogeneous integration of low-dimensional materials andvalidation of their new device architectures, to achieve (1)low metal contactresistance, (2)the construction of a heterogeneously integrated 3D-IC composedof 2D-based field-effect transistor and memory, and (3) The in vertical stackingCNT-based GAA-FET architectures.