Jwu-E Chen

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Research Expertise

VLSI Testing/VLSI CAD

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1 Similar Profiles

5 Finished

晶圓簽署：在晶圓圖分析中，一個可解釋良率、隨機性和顯著性的自動報告系統
Chen, J.
1/08/21 → 31/07/22
Project: Research
An Academic Exploration on Interpreting the Yield and Randomness for Wafer Map Analysis
Chen, J.
1/08/20 → 31/07/21
Project: Research
Identification of the Nonrandom Defects in Volume Production Wafer Maps
Chen, J.
1/08/18 → 31/07/19
Project: Research
Identification of the Defect Uniformity in Volume Production Wafer Maps – Part Ii: Sun Burst on the Scene
Chen, J.
1/08/17 → 31/07/18
Project: Research
Identification of the Defect Uniformity in Volume Production Wafer Maps– Part I: Prior to Dawning
Chen, J.
1/08/16 → 31/07/17
Project: Research

56 Article
37 Conference contribution
17 Conference article
3 Paper
More
- 1 Letter

Multiple Retest Systems for Screening High-Quality Chips
Yeh, C. H. & Chen, J. E., Apr 2023, In: Journal of Electronic Testing: Theory and Applications (JETTA). 39, 2, p. 207-225 19 p.
Research output: Contribution to journal › Article › peer-review

Open Access
1 Scopus citations
Prediction of the Test Yield of Future Integrated Circuits Through the Deductive Estimation Method
Yeh, C. H. & Chen, J. E., 1 Aug 2023, In: Journal of Circuits, Systems and Computers. 32, 12, 2350202.
Research output: Contribution to journal › Article › peer-review
1 Scopus citations
Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments
Yeh, C. H. & Chen, J. E., 1 Jun 2023, In: IEEE Design and Test. 40, 3, p. 45-52 8 p.
Research output: Contribution to journal › Article › peer-review
2 Scopus citations
Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect
Yeh, C. H. & Chen, J. E., 1 Jun 2022, In: Sensors (Switzerland). 22, 11, 4158.
Research output: Contribution to journal › Article › peer-review

Open Access
2 Scopus citations
Using Enhanced Test Systems Based on Digital IC Test Model for the Improvement of Test Yield
Yeh, C. H., Chen, J. E., Chang, C. J. & Huang, T. C., 1 Apr 2022, In: Electronics (Switzerland). 11, 7, 1115.
Research output: Contribution to journal › Article › peer-review

Open Access
2 Scopus citations

Jwu-E Chen

Personal profile

Research Expertise

Fingerprint

Collaborations and top research areas from the last five years

Dive into details

晶圓簽署：在晶圓圖分析中，一個可解釋良率、隨機性和顯著性的自動報告系統

An Academic Exploration on Interpreting the Yield and Randomness for Wafer Map Analysis

Identification of the Nonrandom Defects in Volume Production Wafer Maps

Identification of the Defect Uniformity in Volume Production Wafer Maps – Part Ii: Sun Burst on the Scene

Identification of the Defect Uniformity in Volume Production Wafer Maps– Part I: Prior to Dawning

Multiple Retest Systems for Screening High-Quality Chips

Prediction of the Test Yield of Future Integrated Circuits Through the Deductive Estimation Method

Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments

Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect

Using Enhanced Test Systems Based on Digital IC Test Model for the Improvement of Test Yield

Jwu-E Chen

Personal profile

Research Expertise

Fingerprint

Collaborations and top research areas from the last five years

Projects

Research output