• Source: Scopus
  • Calculated based on no. of publications stored in Pure and citations from Scopus
1984 …2023

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  • 2021

    1st- Order to 2nd Order Threshold Logic Gate Transformation with an Enhanced IPL-based identification Method

    Zheng, L. C., Chang, H. J., Chen, Y. C. & Jou, J. Y., 18 Jan 2021, Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021. Institute of Electrical and Electronics Engineers Inc., p. 469-474 6 p. 3431558. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks

    Chen, Y. G., Hsu, C. W., Chiang, H. Y., Hsieh, T. H. & Jou, J. Y., 2021, Proceedings - 34th IEEE International System-on-Chip Conference, SOCC 2021. Qu, G., Xiong, J., Zhao, D., Muthukumar, V., Reza, M. F. & Sridhar, R. (eds.). IEEE Computer Society, p. 278-283 6 p. (International System on Chip Conference; vol. 2021-September).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions

    Chen, Y. G., Chiang, H. Y., Hsu, C. W., Hsieh, T. H. & Jou, J. Y., 2021, Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., p. 290-291 2 p. (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design

    Chi, H. Y., Chang, H. C., Yang, C. H., Liu, C. N. & Jou, J. Y., 1 Feb 2021, Proceedings of the 2021 Design, Automation and Test in Europe, DATE 2021. Institute of Electrical and Electronics Engineers Inc., p. 1218-1223 6 p. 9474213. (Proceedings -Design, Automation and Test in Europe, DATE; vol. 2021-February).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • 2016

    Chain-based pin count minimization for general-purpose digital microfluidic biochips

    Lei, Y. C., Hsu, C. S., Huang, J. D. & Jou, J. Y., 7 Mar 2016, 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., p. 599-604 6 p. 7428077. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 25-28-January-2016).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • Resource-aware functional ECO patch generation

    Cheng, A. C., Jiang, I. H. R. & Jou, J. Y., 25 Apr 2016, Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016. Institute of Electrical and Electronics Engineers Inc., p. 1036-1041 6 p. 7459462. (Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    11 Scopus citations
  • Wave digital filter based analog circuit emulation on FPGA

    Wu, W., Chen, Y. L., Ma, Y., Liu, C. N. J., Jou, J. Y., Pamarti, S. & He, L., 29 Jul 2016, ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., p. 1286-1289 4 p. 7527483. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 2016-July).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations
  • 2015

    A learning-on-cloud power management policy for smart devices

    Pan, G. Y., Lai, B. C. C., Chen, S. Y. & Jou, J. Y., 5 Jan 2015, 2014 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014 - Digest of Technical Papers. January ed. Institute of Electrical and Electronics Engineers Inc., p. 376-381 6 p. 7001379. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; vol. 2015-January, no. January).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    5 Scopus citations
  • 2014

    A read-write aware DRAM scheduling for power reduction in multi-core systems

    Lai, C. Y., Pan, G. Y., Kuo, H. K. & Jou, J. Y., 2014, 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings. p. 604-609 6 p. 6742957. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    4 Scopus citations
  • 2013

    Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs

    Kuo, H. K., Yen, T. K., Lai, B. C. C. & Jou, J. Y., 2013, 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013. p. 338-343 6 p. 6509618. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    10 Scopus citations
  • 2012

    A formal method to improve SystemVerilog functional coverage

    Cheng, A. C., Yen, C. C. & Jou, J. Y., 2012, 2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012. p. 56-63 8 p. 6418243. (Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    6 Scopus citations
  • Thread affinity mapping for irregular data access on shared cache GPGPU

    Kuo, H. K., Chen, K. T., Lai, B. C. C. & Jou, J. Y., 2012, ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. p. 659-664 6 p. 6165038. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    10 Scopus citations
  • 2011

    Accelerating dynamic peak power analysis using an essential-signal-based methodology

    Shih, C. H., Yen, C. C., Lin, S. T., Lin, H. & Jou, J. Y., 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 140-144 5 p. 5783596. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    1 Scopus citations
  • Equivalence checking of scheduling with speculative code transformations in high-level synthesis

    Lee, C. H., Shih, C. H., Huang, J. D. & Jou, J. Y., 2011, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. p. 497-502 6 p. 5722241. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    36 Scopus citations
  • Mixed non-rectangular block packing for non-Manhattan layout architectures

    Wu, M. C., Chen, H. M. & Jou, J. Y., 2011, Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011. p. 257-262 6 p. 5770734. (Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • 2010

    Expandable MDC-based FFT architecture and its generator for high-performance applications

    Lin, B. C., Wang, Y. H., Huang, J. D. & Jou, J. Y., 2010, Proceedings - IEEE International SOC Conference, SOCC 2010. p. 188-192 5 p. 5784750. (Proceedings - IEEE International SOC Conference, SOCC 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    8 Scopus citations
  • Performance-driven architectural synthesis for distributed register-file microarchitecture considering inter-island delay

    Huang, J. D., Chen, C. I., Hsu, W. L., Lin, Y. T. & Jou, J. Y., 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010. p. 169-172 4 p. 5496717. (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    4 Scopus citations
  • Unleash the parallelism of 3DIC partitioning on GPGPU

    Kuo, H. K., Lai, B. C. C. & Jou, J. Y., 2010, Proceedings - IEEE International SOC Conference, SOCC 2010. p. 127-132 6 p. 5784745. (Proceedings - IEEE International SOC Conference, SOCC 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • 2009

    Hierarchical architecture for network-on-chip platform

    Lin, L. Y., Lin, H. K., Wang, C. Y., Van, L. D. & Jou, J. Y., 2009, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. p. 343-346 4 p. 5158165. (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    1 Scopus citations
  • Multiple-fault diagnosis using faulty-region identification

    Tasi, M. J., Chao, M. C. T., Jou, J. Y. & Wu, M. C., 2009, Proceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009. p. 123-128 6 p. 5116621. (Proceedings of the IEEE VLSI Test Symposium).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    7 Scopus citations
  • 2008

    A code generation algorithm of crosstalk-avoidance code with memory for low-power on-chip bus

    Cheng, K. C. & Jou, J. Y., 2008, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. p. 172-175 4 p. 4542440. (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • Crosstalk-avoidance coding for low-power on-chip bus

    Cheng, K. C. & Jou, J. Y., 2008, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. p. 1051-1054 4 p. 4675037. (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations
  • Message from Symposium Chair and Co-Chair Symposium Chair

    Jou, J. Y. & Wu, C. W., 2008, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. IEEE Computer Society, p. 5 1 p. 4542391. (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • 2007

    A precise bandwidth control arbitration algorithm for hard real-time SoC buses

    Lin, B. C., Lee, G. W., Huang, J. D. & Jou, J. Y., 2007, Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. p. 165-170 6 p. 4196026. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    22 Scopus citations
  • On-chip bus encoding for power minimization under delay constraint

    Lin, T. W., Tu, S. W. & Jou, J. Y., 2007, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 4239402. (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    4 Scopus citations
  • 2006

    A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication

    Chen, C. H., Lee, G. W., Huang, J. D. & Jou, J. Y., 2006, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc., p. 600-605 6 p. 1594751. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2006).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    21 Scopus citations
  • FSM-based transaction-level functional coverage for interface compliance verification

    Su, M. Y., Shih, C. H., Huang, J. D. & Jou, J. Y., 2006, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc., p. 448-453 6 p. 1594726. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2006).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    5 Scopus citations
  • Multi-Project System-on-Chip (MP-SoC): A novel test vehicle for SoC silicon prototyping

    Huang, C. M., Lee, K. J., Yang, C. C., Hu, W. H., Wang, S. S., Chen, J. B., Chen, C. S., Van, L. D., Wu, C. M., Tsai, W. C. & Jou, J. Y., 2006, 2006 IEEE International Systems-on-Chip Conference, SOC. Institute of Electrical and Electronics Engineers Inc., p. 137-140 4 p. 4063036. (2006 IEEE International Systems-on-Chip Conference, SOC).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    12 Scopus citations
  • 2005

    An observability measure to enhance statement coverage metric for proper evaluation of verification completeness

    Jiang, T. Y., Liu, C. N. J. & Jou, J. Y., 2005, Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. Institute of Electrical and Electronics Engineers Inc., p. 323-326 4 p. 1466182. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 1).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    7 Scopus citations
  • An optimum algorithm for compacting error traces for efficient functional debugging

    Yen, C. C. & Jou, J. Y., 2005, Proceedings - Tenth Annual IEEE International High Level Design Validation and Test Workshop, HLDVT'05. p. 177-183 7 p. 1568834. (Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • Communication-driven task binding for multiprocessor with latency insensitive Network-on-Chip

    Lin, L. Y., Wang, C. Y., Huang, P. J., Chou, C. C. & Jou, J. Y., 2005, Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. Institute of Electrical and Electronics Engineers Inc., p. 39-44 6 p. 1466126. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 1).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    18 Scopus citations
  • Formal compliance verification of interface protocols

    Yang, Y. C., Huang, J. D., Yen, C. C., Shih, C. H. & Jou, J. Y., 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT). p. 12-15 4 p. 1500007. (2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT); vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    7 Scopus citations
  • On-chip bus encoding for LC cross-talk reduction

    Huang, J. S., Tu, S. W. & Jou, J. Y., 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT). p. 233-236 4 p. 1500063. (2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT); vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    4 Scopus citations
  • Stimulus generation for interface protocol verification using the non-deterministic extended finite state machine model

    Shih, C. H., Huang, J. D. & Jou, J. Y., 2005, Proceedings - Tenth Annual IEEE International High Level Design Validation and Test Workshop, HLDVT'05. p. 87-93 7 p. 1568819. (Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    9 Scopus citations
  • 2004

    Graph automorphism-based algorithm for determining symmetric inputs

    Chou, C. L., Wang, C. Y., Lee, G. W. & Jou, J. Y., 2004, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004. p. 417-419 3 p. (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • 2003

    An automatic interconnection rectification technique for SoC design integration

    Wang, C. Y., Tung, S. W. & Jou, J. Y., 2003, Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 108-111 4 p. 1195002. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2003-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • An effective physical synthesis technique for multiplier

    Wang, C. Y., Yang, Y. C. & Jou, J. Y., 2003, VLSI 2003 - 2003 20th International Symposium on VLSI Technology, Systems and Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 192-195 4 p. 1252585. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings; vol. 2003-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • An efficient IP-level power model for complex digital circuits

    Hsu, C. Y., Liu, C. N. J. & Jou, J. Y., 2003, Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 610-613 4 p. 1195097. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2003-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations
  • Improved vector compaction for power estimation with multi-sequence sampling technique

    Hsu, C. Y., Liu, C. N. J. & Jou, J. Y., 2003, VLSI 2003 - 2003 20th International Symposium on VLSI Technology, Systems and Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 176-179 4 p. 1252581. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings; vol. 2003-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • Simultaneous floorplanning and buffer block planning

    Hui-Ru Jiang, I., Chang, Y. W., Jou, J. Y. & Chao, K. Y., 2003, Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 431-434 4 p. 1195054. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2003-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    11 Scopus citations
  • 2002

    Effective error diagnosis for RTL designs in HDLs

    Jiang, T. Y., Liu, C. N. J. & Jou, J. Y., 2002, Proceedings of the 11th Asian Test Symposium, ATS 2002. IEEE Computer Society, p. 362-367 6 p. 1181738. (Proceedings of the Asian Test Symposium; vol. 2002-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    6 Scopus citations
  • 2001

    An AVPG for SOC design verification with port order fault model

    Wang, C. Y., Tung, S. W. & Jou, J. Y., 2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. IEEE Computer Society, p. 259-262 4 p. 922034. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; vol. 5).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    6 Scopus citations
  • An efficient design-for-verification technique for HDLs

    Liu, C. N. J., Chen, I. L. & Jou, J. Y., 2001, Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., p. 103-108 6 p. 913288. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2001-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • Automatic functional vector generation using the interacting FSM model

    Liu, C. N. J., Yen, C. C. & Jou, J. Y., 2001, Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001. IEEE Computer Society, p. 372-377 6 p. 915258. (Proceedings - International Symposium on Quality Electronic Design, ISQED; vol. 2001-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • Grouped input power sensitive transition an input sequence compaction technique for power estimation

    Huang, H. L., Chen, Y. R., Jou, J. Y. & Shen, W. Z., 2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. IEEE Computer Society, p. 471-474 4 p. 922087. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; vol. 5).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations
  • On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model

    Wang, C. Y., Tung, S. W. & Jou, J. Y., 2001, Proceedings - 6th IEEE International High-Level Design Validation and Test Workshop, HLDVT 2002. IEEE Computer Society, p. 145-150 6 p. 972821. (Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT; vol. 2001-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • On placement and routing of wafer scale memory

    Sung, L. A., Jiang, I. H. R., Chang, Y. W., Jou, J. Y., Wu, J. C. & Feng, T. S., 2001, ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems. p. 883-887 5 p. 957615. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; vol. 2).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • On tri-state buffer inference in HDL synthesis

    Lin, H. M. & Jou, J. Y., 2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. IEEE Computer Society, p. 45-48 4 p. 921980. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; vol. 5).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • 2000

    A new method for constructing IP level power model based on power sensitivity

    Huang, H. L., Lin, J. Y., Shen, W. Z. & Jou, J. Y., 2000, Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000. p. 135-139 5 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • 1999

    Hierarchical floorplan design on the internet

    Lin, J. H., Jou, J. Y. & Jiang, H. R., 1999, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999. Institute of Electrical and Electronics Engineers Inc., p. 189-192 4 p. 759992. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 1999-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review