Jing-Yang Jou – Projects — National Central University

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Emailjyjouee.ncu.edutw
Websitehttps://www.ncu.edu.tw/tw/pages/show.php?top=1&num=24

Research activity per year

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1 Active
2 Not started
6 Finished

9 results

Active

考量老化且適用於邊緣運算之深度類神經網路加速器設計與優化研究(1/3)
Jou, J.
1/08/21 → 31/07/22
Project: Research
Not started

考量老化且適用於邊緣運算之深度類神經網路加速器設計與優化研究(3/3)
Jou, J.
1/08/23 → 31/07/24
Project: Research
考量老化且適用於邊緣運算之深度類神經網路加速器設計與優化研究(2/3)
Jou, J.
1/08/22 → 31/07/23
Project: Research
Finished
Synthesis and Optimization Techniques for Wdf-Based Analog Circuit Emulators(3/3)
Jou, J.
1/08/20 → 31/07/21
Project: Research
Synthesis and Optimization Techniques for Wdf-Based Analog Circuit Emulators(2/3)
Jou, J.
1/08/19 → 31/07/20
Project: Research
Synthesis and Optimization Techniques for Wdf-Based Analog Circuit Emulators(1/3)
Jou, J.
1/08/18 → 31/07/19
Project: Research
On Analog Circuit Emulation with Digital FPGA Environment(3/3)
Jou, J.
1/08/17 → 31/07/18
Project: Research
On Analog Circuit Emulation with Digital FPGA Environment(2/3)
Jou, J.
1/08/16 → 31/07/17
Project: Research
On Analog Circuit Emulation with Digital FPGA Environment(1/3)
Jou, J.
1/08/15 → 31/07/16
Project: Research